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Integrated Circuit Systems, Inc.
ICS853031
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
FEATURES
* 9 differential 2.5V/3.3V LVPECL/ECL outputs * Selectable differential CLK, nCLK or LVPECL clock inputs * CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL, * PCLK, nPCLK supports the following input types: LVPECL, LVDS, CML, SSTL * Output frequency: 1.6GHz (typical) * Translates any single ended input signal (LVCMOS, LVTTL, GTL) to 3.3V LVPECL levels with resistor bias on nCLK or nPCLK inputs * Output skew: 20ps (typical) * Part-to-part skew: 75ps (typical) * Propagation delay: 875ps (typical) * LVPECL mode operating voltage supply range: VCC = 2.375V to 3.465V, VEE = 0V * ECL mode operating voltage supply range: VCC = 0V, VEE = -2.375V to -3.465V * -40C to 85C ambient operating temperature * Lead-Free package available * Pin compatible with ICS8531-01
GENERAL DESCRIPTION
The ICS853031 is a low skew, high performance 1-to-9 Differential-to-2.5V/3.3V LVPECL/ECL HiPerClockSTM Fanout Buffer and a member of the HiPerClockSTM family of High Performance Clock Solutions from ICS. The ICS853031 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, LVDS, CML, or SSTL input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin.
ICS
Guaranteed output skew and part-to-part skew characteristics make the ICS853031 ideal for high performance workstation and server applications.
BLOCK DIAGRAM
CLK_EN
PIN ASSIGNMENT
VCCO VCCO nQ0 nQ1 nQ2 Q0 Q1 Q2
D Q LE
32 31 30 29 28 27 26 25 Q0 nQ0 Q1 nQ1 Q2 nQ2 Q3 nQ3 Q4 nQ4 Q5 nQ5 Q6 nQ6 Q7 nQ7 Q8 nQ8 VCC CLK nCLK CLK_SEL PCLK nPCLK VEE CLK_EN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Vcco nQ8 Q8 nQ7 Q7 nQ6 Q6 Vcco
CLK nCLK PCLK nPCLK
0 1
24 23 22 21 20 19 18 17
VCCO Q3 nQ3 Q4 nQ4 Q5 nQ5 VCCO
CLK_SEL
ICS853031
32-Lead LQFP 7mm x 7mm x 1.4mm package body Y package Top View
853031AY
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REV. B SEPTEMBER 16, 2004
Integrated Circuit Systems, Inc.
ICS853031
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
Type Description Core supply pin. Pulldown Non-inver ting differential clock input. Inver ting differential clock input. Clock Select input. When HIGH, selects PCLK, nPCLK inputs. Pulldown When LOW, selects CLK, nCLK. LVTTL / LVCMOS interface levels. Pulldown Non-inver ting differential LVPECL clock input. Pullup Inver ting differential LVPECL clock input. Negative supply pin. Synchronizing clock enable. When HIGH, clock outputs follow clock input. When LOW, Q outputs are forced low, nQ outputs are forced high. LVTTL / LVCMOS interface levels. Output supply pins. Differential output pair. LVPECL interface level. Differential output pair. LVPECL interface level. Differential output pair. LVPECL interface level. Differential output pair. LVPECL interface level. Differential output pair. LVPECL interface level. Differential output pair. LVPECL interface level. Differential output pair. LVPECL interface level. Differential output pair. LVPECL interface level. Differential output pair. LVPECL interface level. Pullup
TABLE 1. PIN DESCRIPTIONS
Number 1 2 3 4 5 6 7 8 9, 16, 17, 24, 25, 32 10, 11 12, 13 14, 15 18, 19 20, 21 22, 23 26, 27 28, 2 9 30, 31 Name VCC CLK nCLK CLK_SEL PCLK nPCLK VEE CLK_EN VCCO nQ8, Q8 nQ7, Q7 nQ6, Q6 nQ5, Q5 nQ4, Q4 nQ3 Q3 nQ2, Q2 nQ1, Q1 nQ0, Q0 Input Input Input Input Input Power Input Power Output Output Output Output Output Output Output Output Output Pullup Power
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol RPULLDOWN RPULLUP Parameter Input Pulldown Resistor Input Pullup Resistor Test Conditions Minimum Typical 50 50 Maximum Units K K
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REV. B SEPTEMBER 16, 2004
Integrated Circuit Systems, Inc.
ICS853031
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
Inputs Outputs Selected Sourced CLK, nCLK PCLK, nPCLK CLK, nCLK Q0:Q8 Disabled; LOW Disabled; LOW Enabled nQ0:nQ8 Disabled; HIGH Disabled; HIGH Enabled
TABLE 3A. CONTROL INPUT FUNCTION TABLE
CLK_EN 0 0 1 CLK_SEL 0 1 0
1 1 PCLK, nPCLK Enabled Enabled After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1. In the active mode, the state of the outputs are a function of the CLK, nCLK and PCLK, nPCLK inputs as described in Table 3B.
nCLK, nPCLK CLK, PCLK
Disabled
Enabled
CLK_EN
nQ0:nQ8 Q0:Q8
FIGURE 1. CLK_EN TIMING DIAGRAM
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs CLK or PCLK 0 1 0 1 Biased; NOTE 1 Biased; NOTE 1 nCLK or nPCLK 1 0 Biased; NOTE 1 Biased; NOTE 1 0 1 Q0:Q8 LOW HIGH LOW HIGH HIGH LOW Outputs nQ0:nQ8 HIGH LOW HIGH LOW LOW HIGH Input to Output Mode Differential to Differential Differential to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Polarity Non Inver ting Non Inver ting Non Inver ting Non Inver ting Inver ting Inver ting
NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels".
853031AY
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REV. B SEPTEMBER 16, 2004
Integrated Circuit Systems, Inc.
ICS853031
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
4.6V -4.6V -0.5V to VCC + 0.5V 50mA 100mA -65C to 150C 47.9C/W (0 lfpm) NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Negative Supply Voltage, VEE Inputs, VI Outputs, IO Continuous Current Surge Current Storage Temperature, TSTG Package Thermal Impedance, JA
(Junction-to-Ambient)
Operating Temperature Range, TA -40C to +85C
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.375 TO 3.465V; VEE = 0V
Symbol VCC VCCO I EE Parameter Core Supply Voltage Output Supply Voltage Power Supply Current Test Conditions Minimum 2.375 2.375 Typical 3.3 3.3 Maximum 3.465 3.465 77 Units V V mA
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = 2.375 TO 3.465V; VEE = 0V
Symbol VIH VIL IIH IIL Parameter CLK_EN, CLK_SEL CLK_EN, CLK_SEL Input High Current Input Low Current CLK_EN CLK _S E L CLK_EN CLK_SEL VCC = VIN = 3.465V or 2.625V VCC = VIN = 3.465V or 2.625V VIN = 0V, VCC = 3.465V or 2.625V VIN = 0V, VCC = 3.465V or 2.625V -150 -50 Test Conditions Minimum 2 -0.3 Typical Maximum 3.465 0.8 10 150 Units V V A A A A
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS (CLK, nCLK), VCC = 2.375 TO 3.465V; VEE = 0V
Symbol IIH IIL VPP Parameter Input High Current Input Low Current CLK nCLK CLK nCLK
-50 -150
-40C Min Typ Max
150 10 -50 -150
25C Min Typ Max
150 10 -50 -150
85C Min Typ Max
150 10
Units
A A A A
0.15 1.3 0.15 1.3 0.15 Peak-to-Peak Input Voltage Input High Voltage VEE + 0.7 VCC - 0.85 VEE + 0.7 VCC - 0.85 VEE + 0.7 VCMR Common Mode Range; NOTE 1, 2 NOTE 1: For single ended applications, the maximum input voltage for CLK and nCLK is VCC + 0.3V. NOTE 2: Common mode voltage is defined as VIH.
853031AY
1.3 VCC - 0.85
V V
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REV. B SEPTEMBER 16, 2004
Integrated Circuit Systems, Inc.
ICS853031
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
-40C Min 2.175 1.405 0.15 1.2 Typ 2.275 1.545 0.8 Max 2.38 1.68 1.3 VCC 150 10 -50 -50 Min 2.225 1.425 0.15 1.2 25C Typ 2.295 1.52 0.8 Max 2.37 1.615 1.3 VCC 150 10 -50 Min 2.22 1.44 0.15 1.2 85C Typ 2.295 1.535 0.8 Max 2.365 1.63 1.3 VCC 150 10
TABLE 4D. LVPECL DC CHARACTERISTICS (PCLK, nPCLK), VCC = 3.3V; VEE = 0V
Symbol VOH VOL VPP VCMR IIH IIL Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Input Voltage Input High Voltage Common Mode Range; NOTE 2, 3 PCLK Input High Current nPCLK Input Low Current PCLK Units V V V V A A A A
nPCLK -150 -150 -150 Input and output parameters vary 1:1 with VCC. VEE can vary 0.165V. NOTE 1: Outputs terminated with 50 to VCCO - 2V. NOTE 2: Common mode voltage is defined as VIH. NOTE 3: For single-ended applications, the maximum input voltage for PCLK, nPCLK is VCC + 0.3V.
TABLE 4E. LVPECL DC CHARACTERISTICS (PCLK, nPCLK), VCC = 2.5V; VEE = 0V
Symbol VOH VOL VPP VCMR IIH IIL Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Input Voltage Input High Voltage Common Mode Range; NOTE 2, 3 PCLK Input High Current nPCLK Input Low Current PCLK -40C Min 1.375 0.605 0.15 1.2 Typ 1.475 0.745 0.8 Max 1.58 0.88 1.3 VCC 150 10 -10 -10 Min 1.425 0.625 0.15 1.2 25C Typ 1.495 0.72 0.8 Max 1.57 0.815 1.3 VCC 150 10 -10 Min 1.42 0.64 0.15 1.2 85C Typ 1.495 0.735 0.8 Max 1.565 0.83 1.3 VCC 150 10 Units V V V V A A A A
nPCLK -150 -150 -150 Input and output parameters vary 1:1 with VCC. VEE can vary 0.125V. NOTE 1: Outputs terminated with 50 to VCCO - 2V. NOTE 2: Common mode voltage is defined as VIH. NOTE 3: For single-ended applications, the maximum input voltage for PCLK, nPCLK is VCC + 0.3V.
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REV. B SEPTEMBER 16, 2004
Integrated Circuit Systems, Inc.
ICS853031
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
-40C 25C Max -0.92 -1.62 1.3 0 150 10 -10 -10 Min -1.075 -1.875 0.15 VEE+1.2 Typ -1.005 -1.78 0.8 Max -0.93 -1.685 1.3 0 150 10 -10 Min -1.08 -1.86 0.15 VEE+1.2 85C Typ -1.005 -1.765 0.8 Max -0.935 -1.67 1.3 0 150 10 Units V V V V A A A A
TABLE 4F. ECL DC CHARACTERISTICS (PCLK, nPCLK), VCC = 0V; VEE = -2.375V TO -3.465V
Symbol VOH VOL VPP VCMR IIH IIL Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Input Voltage Input High Voltage Common Mode Range; NOTE 2, 3 PCLK Input High Current nPCLK Input Low Current PCLK Min -1.125 -1.895 0.15 VEE+1.2 Typ -1.025 -1.755 0.8
nPCLK -150 -150 -150 NOTE 1: Outputs terminated with 50 to VCCO - 2V. NOTE 2: Common mode voltage is defined as VIH. NOTE 3: For single-ended applications, the maximum input voltage for PCLK, nPCLK is VCC + 0.3V.
TABLE 5. AC CHARACTERISTICS, VCC = 0V; VEE = -2.375V TO -3.465V OR VCC = 2.375 TO 3.465V; VEE = 0V
Symbol fMAX Parameter Output Frequency Propagation Delay; NOTE 1 PCLK, nPCLK CLK, nCLK 75 0 820 -40C Min Typ >1.6 825 920 20 900 1020 55 785 860 Max Min 25C Typ >1.6 875 960 20 965 1060 55 825 910 Max Min 85C Typ >1.6 925 1010 25 1025 1110 55 Max Units GHz ps ps ps
t PD tsk(o) tsk(pp)
Output Skew; NOTE 2, 4
Par t-to-Par t Skew; NOTE 3, 4 60 150 75 175 75 200 ps Output 20% to 80% 100 215 400 100 225 400 100 215 350 ps tR/tF Rise/Fall Time f 266MHz 48 52 48 52 48 52 % odc Output Duty Cycle 266MHz < f 500MHz 46 54 46 54 46 54 % All parameters measured at 500MHz unless otherwise noted. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
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REV. B SEPTEMBER 16, 2004
Integrated Circuit Systems, Inc.
ICS853031
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
TYPICAL PHASE NOISE
0 -10 -20 -30 -40 -50 -60
155.52MHz Input/Output
RMS Phase Noise Jitter 12K to 20MHz
PHASE NOISE
(dBc) HZ
-70 -80 -90 -100 -110 -120 -130 -140 -150 100 1k 10k 100k 1M 10M 100M
Output Phase Noise: 12k to 20MHz = 339fs Output Phase Noise: 12k to 20MHz = 286fs
OFFSET FREQUENCY (HZ)
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REV. B SEPTEMBER 16, 2004
Integrated Circuit Systems, Inc.
ICS853031
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
2V VCC
VCC, VCCO
Qx
SCOPE
nCLK, nPLK
LVPECL
nQx VEE V EE -0.375V to -1.465V CLK, PLK
V
PP
Cross Points
V
CMR
OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx PART 1 Qx nQy PART 2 Qy
nQx Qx nQy Qy
tsk(pp)
tsk(o)
PART-TO-PART SKEW
OUTPUT SKEW
80% Clock Outputs
80% VSW I N G
nCLK, nPLK CLK, PLK nQ0:nQ8 Q0:Q8
20% tR tF
20%
tPD
OUTPUT RISE/FALL TIME
nQ0:nQ8 Q0:Q8
PROPAGATION DELAY
Pulse Width t
PERIOD
odc =
t PW t PERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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REV. B SEPTEMBER 16, 2004
Integrated Circuit Systems, Inc.
ICS853031
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VCC
R1 1K CLK_IN + V_REF
-
C1 0.1uF R2 1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
TERMINATION
FOR
3.3V LVPECL OUTPUTS
drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to
Zo = 50
3.3V 125 125
FOUT
FIN
Zo = 50
Zo = 50
FOUT
50 1 Z ((VOH + VOL) / (VCC - 2)) - 2 o 50 VCC - 2V RTT
FIN
Zo = 50 84 84
RTT =
FIGURE 3A. LVPECL OUTPUT TERMINATION
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FIGURE 3B. LVPECL OUTPUT TERMINATION
REV. B SEPTEMBER 16, 2004
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Integrated Circuit Systems, Inc.
ICS853031
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
ground level. The R3 in Figure 4B can be eliminated and the termination is shown in Figure 4C.
TERMINATION
FOR
2.5V LVPECL OUTPUT
Figure 4A and Figure 4B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to
2.5V
2.5V
VCCO=2.5V
2.5V
VCCO=2.5V
R1 250
R3 250
+
Zo = 50 Ohm
Zo = 50 Ohm
+
Zo = 50 Ohm
Zo = 50 Ohm
-
2,5V LVPECL Driv er
2,5V LVPECL Driv er
R2 62.5
R4 62.5
R1 50
R2 50
R3 18
FIGURE 4A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 4B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V
VCCO=2.5V
Zo = 50 Ohm
+
Zo = 50 Ohm
2,5V LVPECL Driv er
R1 50
R2 50
FIGURE 4C. 2.5V LVPECL TERMINATION EXAMPLE
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REV. B SEPTEMBER 16, 2004
Integrated Circuit Systems, Inc.
ICS853031
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 5A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation.
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 5A to 5E show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested
3.3V 3.3V
3.3V 1.8V
Zo = 50 Ohm
Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R2 50
R3 50 LVPECL Zo = 50 Ohm
CLK
nCLK
HiPerClockS Input
HiPerClockS Input
R1 50
R2 50
FIGURE 5A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN ICS HIPERCLOCKS LVHSTL DRIVER
BY
FIGURE 5B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVPECL R1 84 R2 84 HiPerClockS Input R4 125
3.3V
3.3V
LVDS_Driv er
Zo = 50 Ohm
CLK
R1 100
Zo = 50 Ohm
nCLK
Receiv er
FIGURE 5C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
FIGURE 5D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVDS DRIVER
BY
3.3V
3.3V
3.3V
LVPECL
Zo = 50 Ohm
C1
R3 125
R4 125
CLK
Zo = 50 Ohm
C2
nCLK
HiPerClockS Input
R5 100 - 200
R6 100 - 200
R1 84
R2 84
R5,R6 locate near the driver pin.
FIGURE 5E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER WITH AC COUPLE
853031AY
BY
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REV. B SEPTEMBER 16, 2004
Integrated Circuit Systems, Inc.
ICS853031
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements.
LVPECL CLOCK INPUT INTERFACE
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 6A to 6E show interface examples for the HiPerClockS PCLK/nPCLK input driven by the most common driver types. The input interfaces suggested
3.3V 3.3V 3.3V R1 50 CML Zo = 50 Ohm PCLK
Zo = 60 Ohm
2.5V
3.3V
2.5V
R3 120
SSTL
R2 50
R4 120
PCLK
Zo = 60 Ohm
Zo = 50 Ohm nPCLK HiPerClockS PCLK/nPCLK
nPCLK
HiPerClockS PCLK/nPCLK
R1 120
R2 120
FIGURE 6A. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN BY A CML DRIVER
FIGURE 6B. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN BY AN SSTL DRIVER
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVPECL R1 84 R2 84
Zo = 50 Ohm
R5 100
C2
3.3V 3.3V
R4 125
3.3V
Zo = 50 Ohm
LVDS
C1
R3 1K
R4 1K
PCLK
nPCLK
HiPerClockS Input
HiPerClockS PCL K/n PC LK
R1 1K
R2 1K
FIGURE 6C. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER
FIGURE 6D. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER
3.3V
3.3V
3.3V
3.3V LVPECL
Zo = 50 Ohm
C1
R3 84
R4 84
PCLK
Zo = 50 Ohm
C2
nPCLK
HiPerClockS PCLK/nPCLK
R5 100 - 200
R6 100 - 200
R1 125
R2 125
FIGURE 6E. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER WITH AC COUPLE
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REV. B SEPTEMBER 16, 2004
Integrated Circuit Systems, Inc.
ICS853031
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
two terminations examples are shown in this schematic. For more termination approaches, please refer to the LVPECL Termination Application Note.
APPLICATION SCHEMATIC EXAMPLE
Figure 7 shows an example of ICS853031 application schematic. In this example, the device is operated at VCC=3.3V. The decoupling capacitor should be located as close as possible to the power pin. The input is driven by a 3.3V LVPECL driver. Only
VCCO = 3.3V
R1 133
VCC = 3.3V
R3 133
VCC = 3.3V
VCCO = 3.3V
Zo = 50 Ohm
Q0
+
R11 50
Zo = 50 Ohm
C7 0.1uF
32 31 30 29 28 27 26 25
nQ0
-
3.3V
Zo = 50 Ohm
CLK_SEL
Zo = 50 Ohm
LVPECL
1 2 3 4 5 6 7 8
VCCO Q0 nQ0 Q1 nQ1 Q2 nQ2 VCCO
R2 82.5
24 23 22 21 20 19 18 17
R4 82.5
VCC CLK nCLK CLK_SEL PCLK nPCLK VEE CLK_EN
VCCO Q3 nQ3 Q4 nQ4 Q5 nQ5 VCCO
R8 50
R9 50
U1 ICS853031
R10 50
9 10 11 12 13 14 15 16
VCCO nQ8 Q8 nQ7 Q7 nQ6 Q6 VCCO
Zo = 50 Ohm
Q8
+
Zo = 50 Ohm
-
nQ8
(U1-9)
VCCO
(U1-16)
(U1-17)
(U1-24)
(U1-25)
(U1-32)
R5 50
R6 50
C1 0.1uF
C2 0.1uF
C3 0.1uF
C4 0.1uF
C5 0.1uF
C6 0.1uF
Optional Y-Termination
R7 50
FIGURE 7. ICS853031 SCHEMATIC EXAMPLE
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REV. B SEPTEMBER 16, 2004
Integrated Circuit Systems, Inc.
ICS853031
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS853031. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS853031 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 77mA = 266.8mW Power (outputs)MAX = 30.2mW/Loaded Output pair If all outputs are loaded, the total power is 9 * 30.94mW = 278.5mW
Total Power_MAX (3.465V, with all outputs switching) = 266.8mW + 278.5mW = 545.3mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.545W * 42.1C/W = 108C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE JA
FOR
32-PIN LQFP FORCED CONVECTION
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W
200
55.9C/W 42.1C/W
500
50.1C/W 39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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3. Calculations and Equations.
ICS853031
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 8.
VCCO
Q1
VOUT
RL
50
VCCO - 2V
FIGURE 8. LVPECL DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CCO
*
For logic high, VOUT = V (V
CCO_MAX
OH_MAX
=V
CCO_MAX
- 0.935V
-V
OH_MAX
) = 0.935V =V - 1.67V
*
For logic low, VOUT = V (V
CCO_MAX
OL_MAX
CCO_MAX
-V
OL_MAX
) = 1.67V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V - (V - 2V))/R ] * (V
L
OH_MAX
CCO_MAX
CCO_MAX
-V
OH_MAX
) = [(2V - (V
CCO_MAX
-V
OH_MAX
))/R ] * (V
L
CCO_MAX
-V
OH_MAX
)=
[(2V - 0.935V)/50] * 0.935V = 19.92mW ))/R ] * (V
L
Pd_L = [(V
OL_MAX
- (V
CCO_MAX
- 2V))/R ] * (V
L
CCO_MAX
-V
OL_MAX
) = [(2V - (V
CCO_MAX
-V
OL_MAX
CCO_MAX
-V
OL_MAX
)=
[(2V - 1.67V)/50] * 1.67V = 11.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.94mW
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ICS853031
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER RELIABILITY INFORMATION
TABLE 7. JAVS. AIR FLOW TABLE
FOR
32 LEAD LQFP
by Velocity (Linear Feet per Minute)
JA
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W
200
55.9C/W 42.1C/W
500
50.1C/W 39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS853031 is: 394
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ICS853031
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
FOR
PACKAGE OUTLINE
AND
DIMENSIONS - Y SUFFIX
32 LEAD LQFP
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 e L ccc 0.45 0 --0.05 1.35 0.30 0.09 MINIMUM NOMINAL 32 --1.40 0.37 -9.00 BASIC 7.00 BASIC 5.60 Ref. 9.00 BASIC 7.00 BASIC 5.60 Ref. 0.80 BASIC 0.60 --0.75 7 0.10 1.60 0.15 1.45 0.45 0.20 MAXIMUM
Reference Document: JEDEC Publication 95, MS-026
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ICS853031
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
Marking ICS853031AY ICS853031AY ICS853031AYL ICS853031AYL Package 32 Lead LQFP 32 Lead LQFP on Tape and Reel 32 Lead "Lead-Free" LQFP 32 Lead "Lead-Free" LQFP on Tape and Reel Count 250 per tray 1000 250 per tray 1000 Temperature -40C to 85C -40C to 85C -40C to 85C -40C to 85C
TABLE 9. ORDERING INFORMATION
Part/Order Number ICS853031AY ICS853031AYT ICS853031AYLF ICS853031AYLFT
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 853031AY
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ICS853031
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
REVISION HISTORY SHEET
Rev
Table T4B T4C T4D
Page 4 4 5
Description of Change LVCMOS Table - changed IIL (CLK_SEL) from -10A min. to -50A min. Differential Table - change IIL (CLK) from -10A min. to -50A min. 3.3V LVPECL Table - change VOH @ 85 to 2.22V min. and 2.295V typical from 2.295V min. and 2.33V typical. Changed IIL (PCLK) from -10A min. to -50A min. 2.5V LVPECL Table - change VOH @ 85 to 1.42V min. and 1.495V typical from 1.495V min. and 1.53V typical. ECL Table - change VOH @ 85 to -1.08V min. and -1.005V typical from -1.005V min. and -0.97V typical. Revised LVPECL Output Termination drawings.
Date
B
T4E T4F
5 6 9
9/10/03
B 2 4 5 6 18
B
12 Revised Figure 6D. 13 Added Schematic Layout T1 Pin Description Table - changed nCLK & nPCLK Type to Pullup (only). T4B LVCMOS Table - added 2.625V in Test Conditions. T4D & E LVPECL DC Characteristics Tables - corrected Note 3. T4F ECL DC Characteristics Tables - corrected Note 3. T9 Ordering Information Table - added Lead-Free par t number.
8/19/04
9/16/04
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